1. Field of the Invention
The present invention relates generally to a fabrication process of a semiconductor device, such as a large scale integrated circuit (LSI) and so forth, and a semiconductor substrate. More specifically, the invention relates to a semiconductor substrate having polysilicon layers which can prevent an active region of the device from being contaminated by a contaminating impurity, and a fabrication process of a semiconductor device utilizing the same.
2. Description of the Prior Art
Recently, associating with increasing of integrated density and lowering of power consumption of an integrated circuit, in the field of dynamic random access memory (DRAM), for example, a longer data retention time is required than that in the prior art, has been required. The data retention time is determined depending upon p-n junction leakage current. The p-n junction leakage current is caused by contamination of semiconductor substrate by penetration of heavy metal impurity, such as Fe, Ni and Cu or so forth, in a device active region of the semiconductor substrate.
As means for removing these heavy metal impurity (contaminating element) from the active region of the device, various gettering technologies have been proposed. Among the gettering technologies, a method for gettering contaminating element to the grain boundary of the polysilicon layer by forming the polycrystalline silicon layer on the back surface of the wafer is effective. This method is generally referred to as PBS (Polysilicon Back Sealing) method, and has been disclosed in U.S. Pat. No. 4,053,335. When gettering of the contaminating element is performed by using the PBS method, the gettering capacity depends upon grain size of the polysilicon layer. It has been well known that the smaller grain size results in higher gettering capacity.
However, for example, during fabrication process of the DRAM, when a step for thermal process at high temperature is included, grain size of the polysilicon layer becomes large through heat treatment to lower performance in gettering.
Thus, as a solution for the problem set forth above, Japanese Unexamined Patent Publication (Kokai) No. Heisei 5-182974 discloses a semiconductor device, in which a first polysilicon layer, a silicon oxide layer and a second polysilicon layer are stacked on the back surface of the wafer. The prior art disclosed in the above-identified publication will be hereinafter referred to as "first prior art".
FIG. 1 is a section showing the semiconductor device in the first prior art. On the back side of a base body 1, a first polysilicon layer 2 is formed in a thickness of approximately 100 nm. The back side of the first polysilicon layer 2 is slightly oxidized to form a silicon oxide layer 3. Then, on the back side of the silicon oxide layer 3, a second polysilicon layer 4 is formed in a thickness of 400 to 900 nm.
In the first prior art as set forth above, the silicon oxide layer 3 is interposed between the first polysilicon layer 2 and the second polysilicon layer 4. Therefore, even when the device is subjected to a heat treatment, growth of polysilicon grains of the second polysilicon layer 4 located at the most back side of the device can be prevented.
Japanese Unexamined Patent Publication No. Heisei 5-286795 discloses another semiconductor device, in which a silicon oxide layer is formed between the base body 1 and the first polysilicon layer 2. The prior art disclosed in the above-identified publication will be hereinafter referred to as "second prior art".
FIG. 2 is a section of the semiconductor device of the second prior art. On the back surface of the base body 5, a first silicon oxide layer 6 is formed in a thickness of 7 to 20 .ANG.. On the back side of the first silicon oxide layer 6, the first polysilicon layer 7 is formed in a thickness of approximately 2000 .ANG.. On the back side of the first polysilicon layer 7, a second silicon oxide layer 8 is formed in a thickness of 7 to 20 .ANG. and the second polysilicon layer 9 are formed in order.
In such second prior art, since the second silicon oxide layer 8 is formed between the first and second polysilicon layers 7 and 9, similar effect to the first prior art can be obtained. On the other hand, since the first silicon oxide layer 6 is formed between the base body 5 and the first polysilicon layer 7, growth of the grains of the first polysilicon layer 7 can also be restricted.
Accordingly, with these method, even in a LSI fabrication process having step of providing heat treatment for the device at high temperature, the semiconductor device which does not lower gettering performance, can be formed.
On the other hand, in the fabrication process of the LSI, such as DRAM or so forth, a plurality of times of high temperature heat treatment is generally performed for the device. Gettering for avoiding the contaminating impurity is consisted of the following three steps as disclosed in J. S. Kang and D. K. Schroder, "Gettering in Silicon" J. Appl. Phys., Vol. 65, No. 8 (1989), pp. 2974-2985. The three steps are consisted of a first step, in which the contaminating impurity is released from an active region of the device, a second step, in which the contaminating impurity is diffused into a gettering layer (polysilicon layers), and a third step, in which the contaminating impurity is captured in the gettering layer.
However, after once capturing the contaminating impurity in the gettering layer, if the gettering layer is subject to high temperature again by the subsequent heat treatment, the impurity may be released from the gettering layer again to diffuse into the active region of the device. Such re-discharging of the impurity is caused when thermal energy kT applied to the device by the heat process is larger than a coupling energy E between defects in the gettering layer and the contaminating impurity.
Accordingly, a plurality of times of high temperature heat treatment encounters a problem to cause growth of grains of the polysilicon layer formed on the back surface of the base body to lower gettering performance, and to re-discharging of the contaminating impurity in the once captured polysilicon layer. In the fabrication process of DRAM and so forth, in which high temperature heat treatment is repeated for a plurality of times, possibility of re-discharging of contaminating impurity once captured in the polysilicon layer to the base body (silicon wafer) becomes high.
In general, a temperature, at which the contaminating impurity is released from the gettering layer, is lower than a temperature, at which the grains of the polysilicon layer is grown. Accordingly, it is important to find a method for effectively preventing growth of the grains of the polysilicon layer. However, it is more important to prevent re-discharging of the contaminating impurity from the polysilicon layer.
In consideration of such point, in the first and second prior art, since growth of grains of the polysilicon layer during fabrication process is prevented, gettering performance of the contaminating impurity may not be lowered. However, these prior art may not prevent re-discharging of the contaminating impurity. Accordingly, in the prior art, in all of the process steps in the LSI fabrication process, it has been difficult to obtain superior gettering effect.
In the PBS method, the contaminating impurity is gettered at the grain boundary of the polysilicon layer formed on the back surface of the base body. As set forth above, at a high temperature T.sub.0, at which the thermal energy kT becomes sufficiently larger than the coupling energy E between the defect presenting at the grain boundary of the polysilicon and the contaminating impurity, the contaminating impurity cannot be captured in the polysilicon layer.
On the other hand, in general, the temperature, at which the contaminating impurity is released from the active region of the device, is lowered than the temperature where the contaminating impurity is released from the gettering layer. Accordingly, at the foregoing temperature T.sub.0, the contaminating impurity uniformly present in the gettering layer and non-gettering layer (base body) at a concentration C.sub.0. Then, when the temperature is lowered, the contaminating impurity is captured at the defect of the grain boundary of the polysilicon layer. On the other hand, at a certain temperature T, when the contaminating impurity concentration in the gettering layer and the contaminating impurity concentration in the non-gettering layer reaches a balanced condition, the contaminating impurity is distributed in the gettering layer and the non-gettering layer. Such activity of the contaminating impurity has been disclosed in Hayamizu et al. "Evaluation of gettering Efficiency in Silicon wafer" TECHNICAL REPORT OF IEICE, SDM 93-105 (1983), pp. 83-89. The concentration of the contaminating impurity in the non-gettering layer can be derived from the following equation (1). EQU C=C.sub.0 /{1+W.sub.2 (K-1)/(W.sub.1 +W.sub.2)} (1)
Here, W.sub.1 shows the thickness of the non-gettering layer, and W.sub.2 shows the thickness of the gettering layer. Also, K is a segregation coefficient of the contaminating impurity between the gettering layer and the non-gettering layer. When the large part of the contaminating impurity is captured in the gettering layer, the concentration of the contaminating impurity in the non-gettering layer becomes lower. Accordingly, smaller value of the contaminating impurity concentration C derived from the equation (1) represents higher gettering performance. Namely, assuming that the thickness of the base body is constant, greater segregation coefficient K and the thickness of the gettering layer W.sub.2, the gettering performance becomes higher. In the PBS method, concretely, greater thickness of the polysilicon layer and smaller the grain size of the polysilicon layer represent higher gettering performance.
However, in general, the thickness of the polysilicon layer used in the PBS method, is approximately 1 .mu.m. When the thickness of the polysilicon layer becomes greater, stress of the base body is loaded to cause deformation of the silicon substrate to affect for the LSI fabrication process. Even when the thickness of the polysilicon layer is increased in the extent not causing deformation in the substrate, it is not possible to enhance gettering performance.
Thus, M. Saito et al., "Gettering of iron using boron doped poly-Si (1), (2), "The Japan Society of Applied Physics and Related Societies (The 41.sup.st Spring Meeting, 1994)", AP 941113-01, 29p-ZD-16, 17, P268-269 discloses that, as means for increasing the value of K, there is a method to add boron in the polysilicon layer. Accordingly, in order to enhance the gettering performance, it is effective to make the grain size of the polysilicon layer smaller and to add boron in the polysilicon layer to make the segregation coefficient K greater.
However, even when the segregation coefficient K is made greater, the contaminating impurity once captured is inherently released and diffused at high temperature as set forth above. Thus, under certain cooling condition, the contaminating impurity can be captured in active region of the device. By this, p-n junction leakage current may be caused to lower the characteristics of the semiconductor device.